mirror of
https://github.com/jhbruhn/eurorack.git
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165 lines
5.8 KiB
Text
165 lines
5.8 KiB
Text
.SUBCKT MCP6001 1 2 3 4 5
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* | | | | |
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* | | | | Output
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* | | | Negative Supply
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* | | Positive Supply
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* | Inverting Input
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* Non-inverting Input
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*
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********************************************************************************
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* Software License Agreement *
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* *
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* The software supplied herewith by Microchip Technology Incorporated (the *
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* "Company") is intended and supplied to you, the Company's customer, for use *
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* soley and exclusively on Microchip products. *
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* *
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* The software is owned by the Company and/or its supplier, and is protected *
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* under applicable copyright laws. All rights are reserved. Any use in *
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* violation of the foregoing restrictions may subject the user to criminal *
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* sanctions under applicable laws, as well as to civil liability for the *
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* breach of the terms and conditions of this license. *
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* *
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* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER *
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* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
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* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
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* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *
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********************************************************************************
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*
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* Macromodel for the MCP6001/2/4 op amp family:
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* MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004
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*
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* Revision History:
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* REV A: 21-Jun-02, Created model
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* REV B: 16-Jul-02, Improved output stage
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* REV C: 03-Jan-03, Added MCP6001
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* REV D: 19-Aug-06, Added over temperature, improved output stage,
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* fixed overdrive recovery time
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* REV E: 27-Jul-07, Updated output impedance for better model stability w/cap load
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* REV F: 09-Jul-12, Added MCP6001R, MCP6001U
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*
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* Recommendations:
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* Use PSPICE (other simulators may require translation)
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* For a quick, effective design, use a combination of: data sheet
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* specs, bench testing, and simulations with this macromodel
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* For high impedance circuits, set GMIN=100F in .OPTIONS
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*
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* Supported:
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* Typical performance for temperature range (-40 to 125) degrees Celsius
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* DC, AC, Transient, and Noise analyses.
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* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
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* open loop gain, voltage ranges, supply current, ... , etc.
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* Temperature effects for Ibias, Iquiescent, Iout short circuit
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* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
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*
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* Not Supported:
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* Some Variation in specs vs. Power Supply Voltage
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* Monte Carlo (Vos, Ib), Process variation
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* Distortion (detailed non-linear behavior)
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* Behavior outside normal operating region
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*
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* Input Stage
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V10 3 10 -500M
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R10 10 11 6.90K
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R11 10 12 6.90K
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C11 11 12 0.2p
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C12 1 0 6.00P
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E12 71 14 POLY(4) 20 0 21 0 26 0 27 0 1.00M 20.1 20.1 1 1
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G12 1 0 62 0 1m
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M12 11 14 15 15 NMI L=2.00U W=42.0U
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M14 12 2 15 15 NMI L=2.00U W=42.0U
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G14 2 0 62 0 1m
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C14 2 0 6.00P
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I15 15 4 50.0U
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V16 16 4 -300M
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GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1))
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V13 3 13 -300M
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GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1))
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R70 1 0 20.6T
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R71 2 0 20.6T
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R72 1 2 20T
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I80 1 2 0.5p
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*
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* Noise, PSRR, and CMRR
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I20 21 20 423U
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D20 20 0 DN1
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D21 0 21 DN1
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G26 0 26 POLY(1) 3 4 110U -49U
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R26 26 0 1
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G27 0 27 POLY(2) 1 0 2 0 -440U 39.7U 39.7U
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R27 27 0 1
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*
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* Open Loop Gain, Slew Rate
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G30 0 30 POLY(1) 12 11 0 1
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R30 30 0 1K
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G31 0 31 POLY(1) 3 4 86 5.25
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R31 31 0 1 TC=2.8m
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GD31 30 31 TABLE {V(30,31)} ((-11,-1)(-10,-10n)(0,0)(1m,1000))
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G32 32 0 POLY(1) 3 4 113.7 3.5
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R32 32 0 1 TC=2.65m
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GD32 30 32 TABLE {V(30,32)} ((-1m,-1000)(0,0)(10,10n)(11,1))
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G33 0 33 30 0 1m
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R33 33 0 1k
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G34 0 34 33 0 425M
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R34 34 0 1K
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C34 34 0 74U
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G37 0 37 34 0 1m
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R37 37 0 1K
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C37 37 0 41.6P
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G38 0 38 37 0 1m
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R38 39 0 1K
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L38 38 39 100U
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E38 35 0 38 0 1
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G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(16,1n))(16.1,1))
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G36 33 0 TABLE {V(35,4)} ((-16.1,-1)((-16,-1n)(0,0)(1,1n))
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*
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* Output Stage
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R80 50 0 100MEG
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G50 0 50 57 96 2
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R58 57 96 0.50
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R57 57 0 750
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C58 5 0 2.00P
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G57 0 57 POLY(3) 3 0 4 0 35 0 0 0.67M 0.67M 1.5M
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GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
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GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
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E55 55 0 POLY(2) 3 0 51 0 -0.7m 1 -40.0M
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E56 56 0 POLY(2) 4 0 52 0 1.2m 1 -37.0M
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R51 51 0 1k
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R52 52 0 1k
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GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))
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GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
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G53 3 0 POLY(1) 51 0 -49U 1M
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G54 0 4 POLY(1) 52 0 -49U -1M
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*
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* Current Limit
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G99 96 5 99 0 1
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R98 0 98 1 TC=-2.8M,2.63U
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G97 0 98 TABLE { V(96,5) } ((-11.0,-10.0M)(-1.00M,-9.9M)(0,0)(1.00M,9.9M)(11.0,10.0M))
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E97 99 0 VALUE { V(98)*((V(3)-V(4))*359M + 310M)}
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D98 4 5 DESD
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D99 5 3 DESD
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*
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* Temperature / Voltage Sensitive IQuiscent
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R61 0 61 100 TC 3.11M 4.51U
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G61 3 4 61 0 1
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G60 0 61 TABLE {V(3, 4)}
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+ ((0,0)(900M,0.0106U)(1.00,0.20U)(1.3,0.63U)
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+ (1.5,0.66U)(1.6,1.06U)(5.5,1.10U))
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*
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* Temp Sensitive offset voltage
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I73 0 70 DC 1uA
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R74 0 70 1 TC=2
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E75 1 71 70 0 1
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*
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* Temp Sensistive IBias
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I62 0 62 DC 1uA
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R62 0 62 REXP 58.2u
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* Voltage on R62 used for G12, G14 in input stage
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*
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* Models
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.MODEL NMI NMOS
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.MODEL DESD D N=1 IS=1.00E-15
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.MODEL DL D N=1 IS=1F
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.MODEL DN1 D IS=1P KF=146E-18 AF=1
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.MODEL REXP RES TCE=10.1
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.ENDS MCP6001
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